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innovative power tm - 1 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. features ? multiple patents pending ? 350ma, pwm step-down dc/dc converter ? eight i 2 c-programmable, low noise ldos ? three optimized for rf section power ? five optimized for bb section power ? li+ battery charger with integrated mosfet ? charger current monitor output (vichg) ? charger on/off control pin ? two n-channel open drain switches ? minimal external components ? i 2 c tm serial interface ? configurable operating modes ? ac-ok and reset outputs ? 55mm, thin-qfn (tqfn55-40) package ? only 0.75mm height ? rohs compliant applications ? gsm or cdma mobile phones general description the patent-pending act5830 is a complete, integrated power management solution that is ideal for mid-high and mobile phones. this device integrates a linear li+ battery charger with an internal power mosfet, a high efficiency 350ma dc/dc converter, eight low dropout linear regulators, a reset output, and two n-channel open drain switches, and an i 2 c serial interface to achieve flexibility for programming ldo outputs and individual on/off control. the charger is a complete, thermally-regulated, stand-alone single-cell linear li+ battery charger that incorporates an internal power mosfet for constant-current/constant -voltage control. the charger includes a variety of value-added features, and it is programmable via the i 2 c-interface to control charging current, termination voltage, along with safety features and operation modes. the act5830 is available in a compact 5mm x 5mm 40-pin thin-qfn package that is just 0.75mm thin. pb-free act5830 rev 2, 20-jan-11 twelve channel pmu for mobile phones system blo ck diagram ?
act5830 rev 2, 20-jan-11 innovative power tm - 2 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? table of contents general informat ion ...................................................................................... p. 01 functional block diagram ................................................................................................. p. 0 3 ordering information ......................................................................................................... p. 04 pin configuration ............................................................................................................. . p. 04 pin descriptions .............................................................................................................. .. p. 05 absolute maximum ratings .............................................................................................. p. 07 system managemen t ........................................................................................ p. 08 electrical characteristics ................................................................................................... p. 08 i 2 c interface electrical characteristics .............................................................................. p. 09 system management register descriptions ..................................................................... p. 10 functional descriptions ..................................................................................................... p. 11 step-down dc/dc con verter ....................................................................... p. 13 electrical characteristics .................................................................................................. p. 13 register descriptions ........................................................................................................ p. 14 typical performance characteristics ............................................................................... p. 16 functional description ...................................................................................................... p . 17 low-dropout linear re gulators .............................................................. p. 19 register descriptions ........................................................................................................ p. 19 typical performance characteristics ................................................................................ p. 23 functional description ...................................................................................................... p . 24 ldo1 ............................................................................................................................... .. p. 25 ldo2 ............................................................................................................................... .. p. 26 ldo3 ............................................................................................................................... .. p. 27 ldo4 ............................................................................................................................... .. p. 28 ldo5 ............................................................................................................................... .. p. 29 ldo6 ............................................................................................................................... .. p. 30 ldo7 ............................................................................................................................... .. p. 31 ldo8 ............................................................................................................................... .. p. 32 single-cell li+ battery charger (chg r) ................................................. p. 33 electrical characteristics ................................................................................................... p. 33 li+ battery charger register descriptions ........................................................................ p. 35 typical performance characteristics ................................................................................ p. 37 functional description ....................................................................................................... p. 38 package informat ion ...................................................................................... p. 41
act5830 rev 2, 20-jan-11 innovative power tm - 3 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional block diagram a ctive-semi charge control vp gp sw nrst chg_in bat 2.9v pre- condition current sense voltage sense 110c thermal regulation out1 4.0v vinuvlo nenchg 4.3v to 6v vbuck body and vsys control to battery ac adaptor or usb + li+ battery nacok vichg batid reset out1 ldo1 out2 ldo2 out3 ldo3 out4 ldo4 out5 ldo5 out6 ldo6 out7 ldo7 out8 ldo8 system control pwr_hold non hf_pwr pwr_on sda scl in1 in2 to ldos to ldos tcxo_en rx_en tx_en odi1 open-drain #1 odi2 od1 od2 open-drain #2 out1 bat voltage reference ref out1 out2 out3 out4 out5 out6 out7 out8 vbuck act5830 g ep
act5830 rev 2, 20-jan-11 innovative power tm - 4 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? 55mm qfn (tqfn55-40) pin configuration part number v buck v ldo1 v ldo2 v ldo3 v ldo4 v ldo5 v ldo6 v ldo7 v ldo8 i charger package pins temperature range act5830qj1cf-t 1.2v 3.0v 1.8v 3. 0v 3.0v 3.0v 3.0v 1. 8v 3.3v 0.45a tqfn55-40 40 -40c to +85c ACT5830QJ182-T 1.2v 3.0v 1.8v 3. 0v 3.0v 2.85v 2.85v 1. 8v 1.5v 0.45a tqfn55-40 40 -40c to +85c ordering information cd c : output voltage options detailed in this table represent st andard voltage options, and are available for samples or production orders. additional output voltage options, as detailed in the output voltage codes table, are available for pro duction subject to minimum order quantities. contact active-semi for more informatio n regarding semi-custom output voltage combinations. d : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of haza rdous substances) standards. vichg chg_in bat ref nrst in2 out4 out6 out8 out2 tx_en batid nenchg nacok nc gp sw sw vp nc vbuck hf_pwr g non in1 out3 out5 out7 out1 rx_en tcxo_en sda scl odi1 od1 od2 odi2 pwr_on pwr_hold nc act5830 ep active- semi
act5830 rev 2, 20-jan-11 innovative power tm - 5 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? pin name description 1 chg_in battery charge supply input. connect a 1f ceramic capacitor from chg_in to g. 2 bat battery charger output. connect th is pin directly to the battery anode (+ terminal), and to in1 and in2 pins. bypass with 10f ceramic capacitor to g. 3 ref reference noise bypass. connect a 0.01f ceramic capacitor from ref to g. this pin is discharged to g in shutdown. 4 nrst active low reset output. nrst asserts low for the reset timeout period of 65ms whenever the act5830 is first enabled. this output is internally connected to out1 via a 15k ? pull-up resistor. 5 in2 input supply to ldo2, ldo4, ldo6, and ldo8. connect to bat and in1. 6 out4 ldo4 output. capable of delivering up to 100m a of output current. output is discharged to ground with 1k ? when disabled. 7 out6 ldo6 output. capable of delivering up to 150m a of output current. output is discharged to ground with 1k ? when disabled. 8 out8 ldo8 output. capable of delivering up to 250m a of output current. output is discharged to ground with 1k ? when disabled. 9 out2 ldo2 output. capable of delivering up to 300m a of output current. output is discharged to ground with 1k ? when disabled. 10 tx_en ldo6 independent on/off control. drive to a logi c high for normal operatio n, and to a logic low to disable. 11 tcxo_en ldo4 independent on/off control. drive to a logi c high for normal operatio n, and to a logic low to disable. 12 sda data input for i 2 c serial interface. data is read on the rising edge of the clock. 13 scl clock input for i 2 c serial interface. data is read on the rising edge of the clock. 14 odi1 digital control for open drain n-channel switch 1. drive to a logic high to turn on the switch. drive to a logic low to turn off the switch. 15 od1 n-channel open?drain output 1. state of output controlled by odi1. 16 od2 n-channel open?drain output 2. state of output controlled by odi2. 17 odi2 digital control for open drain n-channel switch 2. drive to a logic high to turn on the switch. drive to a logic low to turn off the switch. 18 pwr_on push button on/off input. connect a push-button betwe en this pin and bat. there is an internal 200k ? pull down resistor to g. see the system startup & shutdown section for more information. 19 pwr_hold power hold input. drive pwr_hold to a logic high to complete the star tup sequence. drive the pin to a logic low to disable ic. see the system startup & shutdown section for more information. 20 nc no connect. not internally connected. 21 rx_en ldo5 independent on/off control. drive to a logi c high for normal operatio n, and to a logic low to disable. 22 out1 ldo1 output. capable of delivering up to 300m a of output current. output is discharged to ground with 1k ? when disabled. 23 out7 ldo7 output. capable of delivering up to 250m a of output current. output is discharged to ground with 1k ? when disabled. pin descriptions
act5830 rev 2, 20-jan-11 innovative power tm - 6 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? pin name description 24 out5 ldo5 output. capable of delivering up to 150m a of output current. output is discharged to ground with 1k ? when disabled. 25 out3 ldo3 output. capable of delivering up to 100m a of output current. output is discharged to ground with 1k ? when disabled. 26 in1 input supply to ldo1, ldo3, ldo5, and ldo7. connect to bat and in2. 27 non push-button active low open drain output. when pwr_on is low, non is open drain. when pwr_on is high or when in shutdown, non is asse rted low. this output is internally connected to out1 via a 15k ? pull-up resistor. 28 g ground. connect g and gp together at a single point place as close to the ic as possible. 29 hf_pwr hands free input. a high level indicates availability of hands free input. this pin is internally pulled down to g via a 200k ? resistor. connect to a 0.1f capacitor to g to achieve tbdkv (typ) esd protection. 30 vbuck output feedback sense for reg. connect this pi n directly to the output node to connect the internal feedback network to the output voltage. 31 nc no connect. not internally connected. 32 vp power input for reg. connect to bat, in1, and in 2. bypass to gp with a high quality ceramic capacitor placed as close as possible to the ic. 33, 34 sw switching node output for reg. connect this pin to the switching end of the inductor. 35 gp power ground for reg. connect g and gp together at a single point place as close to the ic as possible. 36 nc no connect. not internally connected. 37 nacok chg_in active low status ou tput. nacok is asserted low when v chg_in > 4.0v. 38 nenchg charge enable active low input. drive low or leave floating to enable the charger. drive high to disable the charger. this pin has an internal 200k ? pull-down resistor. 39 batid battery id pin to detect the presence of the batte ry. when the battery is present, the voltage at this pin is lower than 2v, otherwise, it is higher than 2v. 40 vichg charge current monitor. the voltage at this pin is proportional to the charger current, with a gain of 2.47mv/ma. this output becom es high impedance in shutdown. ep ep exposed pad. must be soldered to ground on the pcb. pin descriptions cont?d
act5830 rev 2, 20-jan-11 innovative power tm - 7 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? absolute maximum ratings c c : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability. d : derate 33mw/c above t a = 70c. parameter value unit chg_in to g t < 1ms and duty cycle <1% steady state -0.3 to +7 -0.3 to +6 in1, in2, bat, batid, vichg, scl, sda, pwr_hold, nrst, pwr_on, non, nacok, nenchg, tcxo_en, rx_en, tx_en, odix, odx to g -0.3 to +6 v vp, sw, vbuck to gp -0.3 to +6 v out1, out3, out5, out7 to g -0.3 to v in1 + 0.3 v out2, out4, out6, out8 to g -0.3 to v in2 + 0.3 v gp to g -0.3 to +0.3 v junction to ambient thermal resistance ( ja ) 30 c/w rms power dissipation (t a = 70c) d 2.7 w operating junction temperature (t j ) -40 to 150 c operating temperature range (t a ) -40 to 85 c store temperature -55 to 150 c lead temperature (soldering, 10 sec) 300 c v v ref, hf_pwr to g -0.3 to v bat + 0.3
system management act5830 rev 2, 20-jan-11 innovative power tm - 8 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v bat = v in1 = v in2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit bat operating voltage range 2.6 5.5 v bat uvlo threshold bat voltage rising 2.2 2.35 2.5 v bat uvlo hysteresis bat voltage falling 80 mv bat uvlo delay bat rising 0.1 ms bat falling 5 nrst delay 65 ms reg, ldo1, ldo2 and ldo3 enabled with no load and chgr disabled 0.26 0.5 ma reg, all ldos enabled and chgr disabled. 0.45 0.75 ma ref output voltage 1.24 1.25 1.26 v reference psrr c ref = 0.01f, f = 1khz 75 db odx output on resistance 100ma sink current 4 ? odx output leakage current v odx = v bat 10 a logic high input voltage 1.4 v logic low input voltage 0.4 v logic low output voltage non, nrst, i sink = 5ma 0.3 v logic leakage current v non = v nrst = v chg_in = 4.2v 1 a thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis temperature falling 20 c no load bat supply current
system management act5830 rev 2, 20-jan-11 innovative power tm - 9 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? i 2 c interface electrical characteristics parameter test conditions min typ max unit scl, sda low input voltage 0.4 v scl, sda high input voltage 1.4 v scl, sda leakage current v chg_in = 4.2v 1 a sda low output voltage i ol = 5ma 0.3 v scl clock period, t scl f scl clock freq = 400khz 2.5 s sda data in setup time to scl high, t su 100 ns sda data out hold time after scl low, t hd 300 ns sda data low setup time to scl low, t st start condition 100 ns sda data high hold time after clock high, t sp stop condition 100 ns figure 1: i 2 c serial bus timing note: each session of data transfer is with a start condition, a 7- bits slave address plus a bit to instruct for read or write followed by an acknowledge bit, a register address byte followed by an acknow ledge bit, a data byte followed by an acknowledge bit and a stop condi- tion. the device address, the register address and the data are a ll msb first transferred. each bi t volume is prepared in durin g the scl is low, is latched-in by the rising edge of the scl. the data byte is accepted and is put effective by the time that the last b it volume is latched-in.
system management act5830 rev 2, 20-jan-11 innovative power tm - 10 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? system management register descriptions table 1: global register map output address data (default values) hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 chgr 08h 0 0 0 0 1 0 0 0 0 0 0 0 r v v v chgr 09h 0 0 0 0 1 0 0 1 0 0 r r r r r r chgr 0ah 0 0 0 0 1 0 1 0 r r r r r r r r chgr 0bh 0 0 0 0 1 0 1 1 r r r r r r r 0 ldo3 0ch 0 0 0 0 1 1 0 0 1 r 0 v v v v v ldo5 0dh 0 0 0 0 1 1 0 1 1 r 0 v v v v v ldo7 07h 0 0 0 0 0 1 1 1 r v v v v v v v ldo7 0eh 0 0 0 0 1 1 1 0 1 r 1 r r r r r ldo1 0fh 0 0 0 0 1 1 1 1 1 r 1 v v v v v ldo4 10h 0 0 0 1 0 0 0 0 1 r 0 v v v v v ldo6 11h 0 0 0 1 0 0 0 1 1 r 0 v v v v v ldo8 12h 0 0 0 1 0 0 1 0 1 r 1 v v v v v ldo2 13h 0 0 0 1 0 0 1 1 1 r 0 v v v v v reg 14h 0 0 0 1 0 1 0 0 r v v v v v v v reg 15h 0 0 0 1 0 1 0 1 r r r r r r r 0 reg 16h 0 0 0 1 0 1 1 0 r r r r r r r r reg 17h 0 0 0 1 0 1 1 1 r r r r r r r 1 key: r: read-only bit. no default assigned. v: default values depend on voltage option. default values may vary. note: addresses other than those specified in table 1 may be us ed for factory settings. do not access any registers other than those specified in table 1.
system management act5830 rev 2, 20-jan-11 innovative power tm - 11 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions the act5830 offers a wide array of system management functions that allow it to be configured for optimal performance in a wide range of applications. i2c serial interface at the core of the act5830 ? s flexible architecture is an i 2 c interface that permits optional programming capability to enhance overall system performance. use standard i 2 c write-byte commands to program the act5830 and read-byte commands to read the ic?s status. figure 1: i 2 c serial bus timing provides a standard timing diagram for the i 2 c protocol. the act5830 always operates as a slave device, with address 1010101. system startup & shutdown the act5830 features a flexible enable architecture that allows it to support a variety of push-button enable/disable schemes. although other startup routines are possible, a typical startup and shutdown process would proceed as follows (referring to figure 2): system startup is initia ted whenever one of the following conditions occurs: 1) the user presses t he push-button, asserting pwr_on high, 2) a valid supply (>4v) is connected to the charger input (chg_in), or 3) a headset is connected, asserting hf_pwr high. the act5830qj1cf begins its system startup procedure by enabling reg, ldo7 and ldo8, then ldo1 are enabled when vbuck reaches 87% of its final value; the act5830qj182 begins its system startup procedure by enabling reg, ldo1, ldo7 and ldo8. nrst is asserted low when vout1 reaches 87% of its final value, holding the microprocessor in reset for a user-selectable reset period of 65ms. if vbuck and vout1 are within 13% of their regulation voltages when the reset timer expires, the act5830 de-asserts nrst so that the microprocessor can begin its power up sequence. once the power-up routine is successfully completed, the microprocessor asserts pwr_hold high to keep the act5830 enabled after the push- button is released by the user. once the power-up routine is completed, the remaining ldos can be enabled/disabled via either the i 2 c interface or the tcxo_en (ldo4), rx_en (ldo5), tx_en (ldo6), and pwr_hold (reg and ldo1) pins. this start-up procedure requires that the push- button be held until the microprocessor assumes control of pwr_hold, providing protection against inadvertent momentary assertions of the push- button. if desired, longer ?push-and-hold? times can be easily implemented by simply adding an additional delay before assuming control of pwr_hold. if the microprocessor is unable to complete its power-up rout ine successfully before the user lets go of the push-button, the act5830 will automatically shut itself down. once a successful power-up routine is completed, the user can initiate a shutdown process by pressing the push-button a second time. upon detecting a second assertion of pwr_on (by depressing the push-button), the act5830 asserts non to interrupt the microprocessor which initiates an interrupt service routine that will reveal that the user pressed the push-button. if hf_pwr and chg_ok are both low, the microprocessor then initiates a power-down r outine, the final step of which will be to de-assert pwr_hold, disabling reg and ldo1. open drain outputs the act5830 includes two n-channel open drain outputs (od1 and od2) that can be used for driving external loads such as wleds or a vibrator motor, as shown in the functional diagram. each of the od outputs is enabled when either it's respective odix pin in driven to a logic high. nacok output the act5830's nacok output provides a logic-level indication of the status of the voltage at chg_in. nacok is an open-drain out put which sinks current whenever v chg_in > 4v. thermal overload protection the act5830 integrates thermal overload protection circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions, for example. this circuitry disables all regulators if the act5830 die temperature exceeds 160 c, and prevents the regulators from being enabled until the die temperature drops by 20c (typ), after which a normal startup routine may commence.
system management act5830 rev 2, 20-jan-11 innovative power tm - 12 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? figure 2: startup and shutdown sequence c c : also the out1 for the ACT5830QJ182-T. 2 : apply to the act5830qj1cf only. 2 2
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 13 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v vp = 3.6v, t a = 25c, unless otherwise specified.) c : v nom refers to the nominal output voltage level for v reg as defined by the ordering information section. parameter test conditions min typ max unit vp operating voltage range 3.1 5.5 v vp uvlo threshold input vo ltage rising 2.9 3 3.1 v vp uvlo hysteresis input voltage falling 80 mv standby supply current 110 200 a shutdown supply current reg/on[ ] = [0], v vp = 4.2v 0.1 1 a output voltage regulation accuracy v nom < 1.3v, i out = 10ma -2.4% v nom c +1.8% v nom 1.3v, i out = 10ma -1.2% v nom +1.8% line regulation v vp = max(v nom + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out = 10ma to 350ma 0.0017 %/ma current limit 0.45 0.6 a oscillator frequency v reg 20% of v nom 1.35 1.6 1.85 mhz v reg = 0v 530 khz pmos on-resistance i sw = -100ma 0.45 0.75 ? nmos on-resistance i sw = 100ma 0.3 0.5 ? sw leakage current v vp = 5.5v, v sw = 5.5v or 0v 1 a power good threshold 94 %v nom minimum on-time 70 ns v
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 14 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 14h r vrange vset 15h r mode 16h 17h r r ok on r r r r r r r r r r r r r r r r r r note: see table 1 for default register settings. table 2: control register map table 3: control register bit descriptions r: read-only bits. default values may vary. address name bit access fu nction description 14h vset [5:0] r/w reg output voltage selection see table 4 14h vrange [6] r/w reg voltage range selection 0 min v out = 1.1v 1 min v out = 1.25v 14h [7] r read only 15h mode [0] r/w mode selection 0 pwm/pfm 1 forced pwm 15h [7:1] r read only 16h [7:0] r read only 17h on [0] r/w 0 1 17h ok [1] r reg power-ok 0 output is not ok 1 output is ok 17h [2] r read only 17h [7:3] r read only reg enable reg disable reg enable
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 15 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? register descriptions cont?d table 4: reg/vset[ ] output voltage setting reg/vset [3:0] reg/vset[5:4] reg/vrange[ ] = [0] reg/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 n/a n/a 1.455 1.860 1. 250 2.050 2.850 3.650 0001 n/a n/a 1.480 1.890 1. 300 2.100 2.900 3.700 0010 n/a 1.100 1.505 1.915 1. 350 2.150 2.950 3.750 0011 n/a 1.125 1.530 1.940 1. 400 2.200 3.000 3.800 0100 n/a 1.150 1.555 1.965 1. 450 2.250 3.050 3.850 0101 n/a 1.175 1.585 1.990 1. 500 2.300 3.100 3.900 0110 n/a 1.200 1.610 2.015 1. 550 2.350 3.150 3.950 0111 n/a 1.225 1.635 2.040 1. 600 2.400 3.200 4.000 1000 n/a 1.255 1.660 2.065 1. 650 2.450 3.250 4.050 1001 n/a 1.280 1.685 2.090 1. 700 2.500 3.300 4.100 1010 n/a 1.305 1.710 2.115 1. 750 2.550 3.350 4.150 1011 n/a 1.330 1.735 2.140 1. 800 2.600 3.400 4.200 1100 n/a 1.355 1.760 2.165 1. 850 2.650 3.450 4.250 1101 n/a 1.380 1.785 2.190 1. 900 2.700 3.500 4.300 1110 n/a 1.405 1.810 2.200 1. 950 2.750 3.550 4.350 1111 n/a 1.430 1.835 2.245 2. 000 2.800 3.600 4.400 (n/a): not available
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 16 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? typical performance characteristics (v inx = 3.6v, c outx = 1f, t a = 25c unless otherwise specified.) act5830-001 reg efficiency vs. load output current (ma) 10 100 1000 80 50 55 70 65 efficiency (%) 1 90 95 reg mosfet resistance r dson (m ? ) vp1 voltage (v) 600 0 act5830-004 5.5 5.0 4.5 4.0 3.5 3.0 2.5 500 550 400 450 300 350 200 250 100 150 50 pmos nmos reg output voltage vs. temperature v reg voltage (v) 1.812 1.788 temperature (c) act5830-003 -20 -40 0 20 40 60 1.810 1.808 1.806 1.804 1.802 1.800 1.798 1.796 1.794 1.792 1.790 i out1 = 35ma 85 reg load regulation load regulation error (%) 0.2 400 output current (ma) act5830-002 50 100 150 200 250 300 350 0.0 -0.2 -0.4 -0.6 -0.8 3.6v 4.2v 0 act5830-005 ch1 ch2 reg load transient response ch1: v out1 , 50mv/div (ac coupled) ch2: i out1 , 200ma/div time: 200s/div 0ma act5830-006 ch1 ch2 reg load transient response 0ma ch1: v out1 , 50mv/div (ac coupled) ch2: i out1 , 200ma/div time: 200s/div 60 75 85 3.6v 4.0v -1.0
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 17 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions general description reg is a fixed-frequency, current-mode, synchronous pwm step-down converters that achieves a peak efficiency of up to 97%. reg is capable of supplying up to 350ma of output current and operates with a fixed frequency of 1.6mhz, minimizing noise in sensitive applications and allowing the use of small external components. reg is available with a variety of standard and custom output voltages, and may be software- controlled via the i 2 c interface by systems that require advanced power management functions. 100% duty cycle operation reg is capable of operating at up to 100% duty cycle. during 100% duty-cycle operation, the high- side power mosfet is held on continuously, providing a direct connection from the input to the output (through the inducto r), ensuring the lowest possible dropout voltage in battery-powered applications. synchronous rectification reg features an integrated n-channel synchronous rectifier, which maximizes efficiency and minimizes the total solution size and cost by eliminating the need for an external rectifier. enabling and disabling reg enable/disable functionality is typically implemented as part of a controlled enable/disable scheme utilizing nmstr and other sy stem control features of the act5830. reg is automatically enabled whenever either of the following conditions are met: 1) hf_pwr is asserted high, or 2) pwr_on is asserted high, or 3) pwr_hold is asserted high. when none of these conditions are true, or if reg/on[ ] bit is set to [0], reg is disabled, and its quiescent supply current drops to less than 1a. programming the output voltage by default, reg powers up and regulates to its default output voltage. once the system is enabled, reg?s output voltage may be programmed to a different value, typically in order to reduce the power consumption of a microprocessor in standby mode. program the output voltage via the i 2 c serial interface by writing to the reg/vset[ ] register. programmable operating mode by default, reg operates in fixed-frequency pwm mode at medium to heavy loads, then transitions to a proprietary power-saving mode at light loads in order to save power. in applications where low noise is critical, fo rce fixed-frequency pwm operation across the entire load current range, at the expense of light-load efficiency, by setting the reg/mode[ ] bit to [1]. power-ok reg features a power-ok status bit that can be read by the system micr oprocessor. if the output voltage is lower than the power-ok threshold, typically 6% below the programmed regulation voltage, reg/ok[ ] will clear to 0. soft-start reg includes internal soft-start circuitry, and enabled its output voltage tracks an internal 80s soft-start ramp so that it powers up in a monotonic manner that is independent of loading. compensation reg utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. no compensation design is required, simply follow a few simple guidelines described below when choosing external components. input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 2.2f ceramic input capacitor is recommended for most applications. output capacitor selection for most applications, a 10f ceramic output capacitor is recommended. although reg was designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr, low-esr tantalum capacitors can provide acceptable results as well.
step-down dc/dc converter act5830 rev 2, 20-jan-11 innovative power tm - 18 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions cont?d inductor selection reg utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. reg was optimized for operation with a 3.3h inductor, although inductors in the 2.2h to 4.7h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current of the application by at least 30%. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dc exhibits discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of vias if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star-ground configurati on, and this point should be connected to the backside ground plane with multiple vias. the output node should be connected to the vbuck pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance.
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 19 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? address data d7 d6 d5 d4 d3 d2 d1 d0 07h r vrange7 0fh dis1 ok1 on1 vset1 13h dis2 ok2 on2 vset2 0eh dis7 ok7 on7 r r r r r 12h dis8 ok8 on8 vset8 0ch dis3 ok3 on3 vset3 10h dis4 ok4 on4 vset4 0dh dis5 ok5 on5 vset5 11h dis6 ok6 on6 vset6 vset7 table 5: ldo control register map register descriptions note: see table 1 for default register settings. table 6: ldo control register bit descriptions address name bit access fu nction description 07h vset7 [5:0] r/w ldo7 output voltage selection see table 8 07h vrange7 [6] r/w reg voltage range selection 0 min v out = 0.645v 1 min v out = 1.25v 07h [7] r read only 0fh vset1 [4:0] r/w ldo1 output voltage selection see table 7 0fh on1 [5] r/w ldo1 enable 0 ldo1 disable 1 ldo1 enable 0fh ok1 [6] r ldo1 power-ok 0 output out of regulation 1 output in regulation 0fh dis1 [7] r/w ldo1 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 13h vset2 [4:0] r/w ldo2 output voltage selection see table 7 13h on2 [5] r/w ldo2 enable 0 ldo2 disable 1 ldo2 enable 13h ok2 [6] r ldo2 power-ok 0 output out of regulation 1 output in regulation 13h dis2 [7] r/w ldo2 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 12h vset8 [4:0] r/w ldo8 output voltage selection see table 7
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 20 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? table 6: ldo control register bit descriptions (cont?d) address name bit access fu nction description 12h on8 [5] r/w ldo8 enable 0 ldo8 disable 1 ldo8 enable 12h ok8 [6] r ldo8 power-ok 0 output out of regulation 1 output in regulation 12h dis3 [7] r/w ldo8 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 0ch vset3 [4:0] r/w ldo3 output voltage selection see table 7 0ch on3 [5] r/ w ldo3 enable 0 ldo3 disable 1 ldo3 enable 0ch ok3 [6] r ldo3 power-ok 0 output out of regulation 1 output in regulation 0ch dis3 [7] r/w ldo3 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 10h vset4 [4:0] r/w ldo4 output voltage selection see table 7 10h on4 [5] r/w ldo4 enable 0 ldo4 disable 1 ldo4 enable 10h ok4 [6] r ldo4 power-ok 0 output out of regulation 1 output in regulation 10h dis4 [7] r/w ldo4 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 0dh vset5 [4:0] r/w ldo5 output voltage selection see table 7 0dh on5 [5] r/w ldo5 enable 0 ldo5 disable 1 ldo5 enable 0dh ok5 [6] r ldo5 power-ok 0 output out of regulation 1 output in regulation 0dh dis5 [7] r/w ldo5 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 11h vset6 [4:0] r/w ldo6 output voltage selection see table 7 11h on6 [5] r/w ldo6 enable 0 ldo6 disable 1 ldo6 enable register descriptions cont?d
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 21 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? register descriptions cont?d table 6: ldo control register bit descriptions (cont?d) address name bit access fu nction description 11h ok6 [6] r ldo6 power-ok 0 output out of regulation 1 output in regulation 11h dis6 [7] r/w ldo6 output discharge enable 0 output high-z in shutdown 1 output discharge enabled 0eh [4:0] r read only 0eh on7 [5] r/w ldo7 enable 0 ldo7 disable 1 ldo7 enable 0eh ok7 [6] r ldo7 power-ok 0 output out of regulation 1 output in regulation 0eh dis7 [7] r/w ldo7 output discharge enable 0 output high-z in shutdown 1 output discharge enabled
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 22 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? ldox/vsetx[2:0] 00 01 10 11 000 1.4 2.15 2.55 3.0 001 1.5 2.20 2.60 3.1 010 1.6 2.25 2.65 3.2 011 1.7 2.30 2.70 3.3 100 1.8 2.35 2.75 3.4 101 1.9 2.40 2.80 3.5 110 2.0 2.45 2.85 3.6 111 2.1 2.50 2.90 3.7 ldox/vsetx[4:3] table 7: ldo1234568/vset[ ] out put voltage settings table 8: ldo7/vset[ ] output voltage settings register descriptions cont?d ldo7/vset [3:0] ldo7/vset[5:4] ldo7/vrange[ ] = [0] ldo7/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 0.645 1.050 1.455 1.860 1.250 2.050 2.850 3.650 0001 0.670 1.075 1.480 1.890 1.300 2.100 2.900 3.700 0010 0.695 1.100 1.505 1.915 1.350 2.150 2.950 n/a 0011 0.720 1.125 1.530 1.940 1.400 2.200 3.000 n/a 0100 0.745 1.150 1.555 1.965 1.450 2.250 3.050 n/a 0101 0.770 1.175 1.585 1.990 1.500 2.300 3.100 n/a 0110 0.795 1.200 1.610 2.015 1.550 2.350 3.150 n/a 0111 0.820 1.225 1.635 2.040 1.600 2.400 3.200 n/a 1000 0.845 1.255 1.660 2.065 1.650 2.450 3.250 n/a 1001 0.870 1.280 1.685 2.090 1.700 2.500 3.300 n/a 1010 0.895 1.305 1.710 2.115 1.750 2.550 3.350 n/a 1011 0.920 1.330 1.735 2.140 1.800 2.600 3.400 n/a 1100 0.950 1.355 1.760 2.165 1.850 2.650 3.450 n/a 1101 0.975 1.380 1.785 2.190 1.900 2.700 3.500 n/a 1110 1.000 1.405 1.810 2.200 1.950 2.750 3.550 n/a 1111 1.025 1.430 1.835 2.245 2.000 2.800 3.600 n/a (n/a): not available
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 23 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? typical performance characteristics ldo load regulation (v inx = 3.6v, c outx = 1f, t a = 25c unless otherwise specified.) act5830-007 power supply rejection ratio frequency (khz) 1 10 100 60 20 30 50 40 psrr (db) c out = 1f i load = 150ma ldo5 0.1 act5830-008 load current (ma) 150 250 350 200 50 0 dropout voltage (mv) 250 0 100 50 150 200 dropout voltage vs. load current ldo1 i out (ma) 100 200 250 150 50 0 v out (v) 0.0% -1.5% -1.0% -0.5% act5830-009 70 80 100 300 ldo8 ldo5 ldo3 ldo8 ldo5 ldo3 ldo1 300 350 act5830-010 ldo output voltage noise ch1 ch1: v outx , 1mv/div time: 10ms/div
low-dropout line ar regulators act5830 rev 2, 20-jan-11 innovative power tm - 24 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions general description the act5830 features eight high performance, low- dropout, low-noise and low quiescent current ldos with high psrr. programming output voltages (vset) all ldos feature independently-programmable output voltages that are set via the i 2 c serial interface, increasing the act5830 flexibility while reducing total solution size and cost. set the output voltage by writing to the ldox/vset[ _ ] register. see table 7: ldo1234568/vset[4:0] and table 8: ldo7/vset[ _ ] output voltage settings for a detailed description of voltage programming options. enabling and disabling ldos for information regarding enabling and disabling the ldos during the startup and shutdown sequence section. once the startup routine is completed the remaining ldos can be enabled/disabled via either the i 2 c interface or the tcxo_en (ldo4), rx_en (ldo5), tx_en (ldo6), and pwr_hold (ldo1, ldo2, ldo3, ldo7, and ldo8). reference bypass pin the act5830 contains a conference bypass pin which filters noise from the reference, providing a low-noise voltage reference to the ldos. bypass ref to g with a 0.01f ceramic capacitor. compensation and stability the ldos need an output capacitor for stability. this capacitor should be connected directly between the output and g pin, as close to the output as possible, and with a short, direct connection to maximize device?s performance. to ensure best performance fo r the device, the output capacitor should have a minimum capacitance of 1f, and esr value between 10m ? and 500m ? . high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. see the capacitor selection section for more information. capacitor selection the input capacitor reduces peak currents and noise at the voltage source. connect a low esr bulk capacitor (>1 f suggested) to the input. select this bulk capacitor to meet the input ripple requirements and voltage rating, rather than capacitor size. pcb layout considerations the act5830?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dc. ref is a filtered reference noise, and internally has a direct connection to the linear regulator controller. any noise injected onto ref will directly affect the outputs of the linear regul ators, and therefore special care should be taken to ensure that no noise is injected to the outputs via ref. as with the ldo output capacitors, the ref by pass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of vias whenever possible. noisy nodes, such as from the dc/dc, should be routed as far away from ref as possible.
ldo1 act5830 rev 2, 20-jan-11 innovative power tm - 25 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in1 = 3.6v, c out1 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in1 input rising 2.9 3 3.1 v uvlo hysteresis v in1 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in1 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out1 = 1ma to 300ma -0.004 %/ma power supply rejection ratio f = 1khz, i out1 = 300ma, c out1 = 1f 60 db f = 10khz, i out1 = 300ma, c out1 = 1f 50 supply current per output ldo1 enabled 20 a ldo1 disabled 0 dropout voltage 2 i out1 = 150ma 100 200 mv output current 300 ma current limit v out1 = 95% of regulation voltage 330 580 ma current limit short circuit fold- back v out1 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out1 , hysteresis = -1% 89 % output noise c out1 = 10f, f = 10hz to 100khz 40 v rms stable c out1 1 20 f c : v nom refers to the nominal output voltage level for ldo1 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between i nput and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo2 act5830 rev 2, 20-jan-11 innovative power tm - 26 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in2 = 3.6v, c out2 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in2 input rising 2.9 3 3.1 v uvlo hysteresis v in2 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in2 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out2 = 1ma to 300ma -0.004 %/ma power supply rejection ratio f = 1khz, i out2 = 300ma, c out2 = 1f 60 db f = 10khz, i out2 = 300ma, c out2 = 1f 50 supply current per output ldo2 enabled 20 a ldo2 disabled 0 dropout voltage 2 i out2 = 150ma 100 200 mv output current 300 ma current limit v out2 = 95% of regulation voltage 330 580 ma current limit short circuit foldback v out2 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out2 , hysteresis = -1% 89 % output noise c out2 = 10f, f = 10hz to 100khz 40 v rms stable c out2 1 20 f c : v nom refers to the nominal output voltage level for ldo2 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo3 act5830 rev 2, 20-jan-11 innovative power tm - 27 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in1 = 3.6v, c out3 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in1 input rising 2.9 3 3.1 v uvlo hysteresis v in1 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in3 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out3 = 1ma to 100ma -0.004 %/ma power supply rejection ratio f = 1khz, i out3 = 100ma, c out3 = 1f 60 db f = 10khz, i out3 = 100ma, c out3 = 1f 50 supply current per output ldo3 enabled 40 a ldo3 disabled 0 dropout voltage 2 i out3 = 50ma 100 200 mv output current 100 ma current limit v out3 = 95% of regulation voltage 115 180 ma current limit short circuit foldback v out3 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out3 , hysteresis = -1% 89 % output noise c out3 = 10f, f = 10hz to 100khz 40 v rms stable c out3 1 20 f c : v nom refers to the nominal output voltage level for ldo3 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo4 act5830 rev 2, 20-jan-11 innovative power tm - 28 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in2 = 3.6v, c out4 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in2 input rising 2.9 3 3.1 v uvlo hysteresis v in2 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in4 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out4 = 1ma to 100ma -0.004 %/ma power supply rejection ratio f = 1khz, i out4 = 100ma, c out4 = 1f 70 db f = 10khz, i out4 = 100ma, c out4 = 1f 60 supply current per output ldo4 enabled 40 a ldo4 disabled 0 dropout voltage 2 i out4 = 50ma 100 200 mv output current 100 ma current limit v out4 = 95% of regulation voltage 115 180 ma current limit short circuit foldback v out4 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out4 , hysteresis = -1% 89 % output noise c out4 = 10f, f = 10hz to 100khz 40 v rms stable c out4 1 20 f c : v nom refers to the nominal output voltage level for ldo4 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo5 act5830 rev 2, 20-jan-11 innovative power tm - 29 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in1 = 3.6v, c out5 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in1 input rising 2.9 3 3.1 v uvlo hysteresis v in1 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in5 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out5 = 1ma to 150ma -0.004 %/ma power supply rejection ratio f = 1khz, i out5 = 150ma, c out5 = 1f 70 db f = 10khz, i out5 = 150ma, c out5 = 1f 60 supply current per output ldo5 enabled 40 a ldo5 disabled 0 dropout voltage 2 i out5 = 80ma 100 200 mv output current 150 ma current limit v out5 = 95% of regulation voltage 165 260 ma current limit short circuit foldback v out5 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out5 , hysteresis = -1% 89 % output noise c out5 = 10f, f = 10hz to 100khz 40 v rms stable c out5 1 20 f c : v nom refers to the nominal output voltage level for ldo5 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo6 act5830 rev 2, 20-jan-11 innovative power tm - 30 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in2 = 3.6v, c out6 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in2 input rising 2.9 3 3.1 v uvlo hysteresis v in2 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in6 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out6 = 1ma to 150ma -0.004 %/ma power supply rejection ratio f = 1khz, i out6 = 150ma, c out6 = 1f 70 db f = 10khz, i out6 = 150ma, c out6 = 1f 60 supply current per output ldo6 enabled 40 a ldo6 disabled 0 dropout voltage 2 i out6 = 80ma 100 200 mv output current 150 ma current limit v out6 = 95% of regulation voltage 165 260 ma current limit short circuit foldback v out6 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out6 , hysteresis = -1% 89 % output noise c out6 = 10f, f = 10hz to 100khz 40 v rms stable c out6 1 20 f c : v nom refers to the nominal output voltage level for ldo6 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo7 act5830 rev 2, 20-jan-11 innovative power tm - 31 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in1 = 3.6v, c out7 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in1 input rising 2.9 3 3.1 v uvlo hysteresis v in1 input falling 0.1 v output voltage accuracy t a = 25c v nom < 1.3v, i out = 10ma -2.4 0 2 % v nom 1.3v, i out = 10ma -1.2 0 2 v nom < 1.3v, i out = 10ma -5 0 3 v nom 1.3v, i out = 10ma -2.5 0 3 line regulation error v in7 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out7 = 1ma to 250ma -0.004 %/ma power supply rejection ratio f = 1khz, i out7 = 250ma, c out7 = 1f 60 db f = 10khz, i out7 = 250ma, c out7 = 1f 50 supply current per output ldo7 enabled 20 a ldo7 disabled 0 dropout voltage 2 i out7 = 100ma 100 200 mv output current 250 ma current limit v out7 = 95% of regulation voltage 275 410 ma current limit short circuit foldback v out7 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out7 , hysteresis = -1% 89 % output noise c out7 = 10f, f = 10hz to 100khz 40 v rms stable c out7 1 20 f t a = -40c to 85c c : v nom refers to the nominal output voltage level for ldo7 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
ldo8 act5830 rev 2, 20-jan-11 innovative power tm - 32 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v in2 = 3.6v, c out8 = 1f, t a = 25c unless otherwise specified.) parameter test conditions min typ max unit input supply range 3.1 5.5 v input under voltage lockout v in2 input rising 2.9 3 3.1 v uvlo hysteresis v in2 input falling 0.1 v output voltage accuracy t a = 25c -1.2 0 2 % t a = -40c to 85c -2.5 0 3 line regulation error v in8 = max (v nom 1 + 0.5v, 3.1v) to 5.5v 0 mv/v load regulation error i out8 = 1ma to 250ma -0.004 %/ma power supply rejection ratio f = 1khz, i out8 = 250ma, c out8 = 1f 60 db f = 10khz, i out8 = 250ma, c out8 = 1f 50 supply current per output ldo8 enabled 20 a ldo8 disabled 0 dropout voltage 2 i out8 = 100ma 100 200 mv output current 250 ma current limit v out8 = 95% of regulation voltage 275 410 ma current limit short circuit foldback v out8 = 0v 0.45 x i lim internal soft-start 100 s power good flag high threshold v out8 , hysteresis = -1% 89 % output noise c out8 = 10f, f = 10hz to 100khz 40 v rms stable c out8 1 20 f c : v nom refers to the nominal output voltage level for ldo8 as defined by the ordering information section. 2 : dropout voltage is defined as the different voltage between input and output when the output voltage drops 100mv below the re gu- lation voltage at 1v differential voltage.
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 33 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? electrical characteristics (v chg_in = 5v, v bat = 3.6v, vset[ ] = [0101], iset[ ] = [0101], t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit chg_in operating range 4.2 6 v uvlo threshold chg_in volt age rising 3.75 4 4.25 v uvlo hysteresis chg_in voltage falling 500 mv battery termination voltage 4.179 4.200 4.221 v line regulation v chg_in = 4.5v to 5.5v, i bat = 10ma 0.2 %/v pmos on resistance 0.3 0.5 ? charge current v bat = 3.8v 450 500 550 ma vichg voltage v vichg /i bat 2.3 mv/ma precondition charge current v bat = 2.8v 35 50 65 ma precondition threshold voltage v bat voltage rising 2.75 2.9 3.0 v precondition threshold hysteresis v bat voltage falling 150 mv end-of-charge current threshold v bat = 4.1v 50 ma end-of-charge qualification period 32 ms charge restart threshold vset[ ] - v bat , v bat falling 200 mv batid high input voltage v batid voltage rising 2.5 v batid low input voltage v batid voltage falling 2 v batid leakage current v chg_in = 4.5v 1 a thermal regulation threshold 105 c bat reserve leakage current sleep, suspend, or timer-fault state 0.4 5 a v nenchg > 1.4v 65 100 a sleep, suspend, or timer-fault state 200 500 a precondition, fast-charge, or top-off state 0.8 1.2 ma precondition timeout period timoset[ ] = [00] 1 hr timoset[ ] = [01] 1.43 hr timoset[ ] = [10] 2 hr timoset[ ] = [11] infinite total charging timeout period timoset[ ] = [00] 3 hr timoset[ ] = [01] 4.3 hr timoset[ ] = [10] 6 hr timoset[ ] = [11] infinite chg_in supply current
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 34 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? figure 3: battery charger algorithm
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 35 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? address name bit access fu nction description 08h vset [2:0] r/w charge termination voltage selection see table 11 08h [3] r read only 08h iset [7:4] r/w maximum charge current selection see table 10 09h vinpok [0] r input supply power-ok 0 input power is not ok 1 input power is ok 09h chgrstat [1] r charging status 0 not charging 1 charging 09h [2] r read only 09h timoflt [3] r timeout fault 0 no timeout fault 1 timeout fault 09h batflt [4] r battery removed fault 0 battery not removed 1 battery removed 09h [5] r read only 09h timoset [7:6] r/w charge timeout select see table 12 0ah [7:0] r read only 0bh suschg [0] r/w suspend charging 0 charging enabled 1 charging disabled 0bh chgrok [1] r charge status 0 charging error occurred 1 charging ok 0bh [7:2] r read only table 9: battery charger (chgr) control register bit descriptions li+ battery charger re gister descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 08h iset r 09h timoset r batflt timoflt r chgrstat vinpok 0ah r r r r r 0bh r r r r r r chgrok suschg vset r r r table 8: battery charger (chgr) control register map note: see table 1 for default register settings. r: read-only bits. default values may vary.
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 36 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? chgr/iset[3:0] fast charge current settings (ma) 0000 100 0001 300 0010 350 0011 400 0100 450 (default) 0101 500 0110 550 0111 600 1000 650 1001 700 1010 750 1011 800 1100 850 1101 900 1110 950 1111 1000 li+ battery charge register descriptions cont?d chgr/vset[3:0] charge termination voltage (v) 000 4.10 001 4.12 010 4.14 011 4.16 100 4.18 101 4.20 (default) 110 4.22 111 4.24 table 10: chgr charge current settings table 11: charge termination voltage settings
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 37 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? typical performanc e characteristics (c outx = 1f x7r, v bat = v inx = v outx + 0.5v, t a = 25c, unless otherwise specified.) vichg voltage vs. i bat v vichg (mv) i bat (ma) 0 act5830-012 1000 0 200 400 600 250 800 500 750 1000 1250 1500 1750 2000 2250 v chg_in = 5v v batid = 2.5v iset[3:0] = [1111] v bat (v) temperature (c) 4.10 battery termination voltage vs. temperature act5830-011 80 -20 0 20 40 100 60 -40 120 4.31 4.13 4.16 4.25 4.28 i bat (a) bat reverse leakage current vs. temperature temperature (c) 4 5 3 2 act5830-015 80 -20 0 20 40 100 60 -40 120 mosfet resistance vs. temperature r dson (m ? ) 325 temperature (c) 315 305 295 280 act5830-014 80 -20 0 20 40 100 60 -40 120 285 290 300 310 320 v chg_in = 0v or floating v bat = 5v iset[3:0] = [1111] precondition threshold voltage vs. temperature v precondition (v) 3.0 temperature (c) 80 3.1 2.8 2.7 -20 0 20 40 100 60 act5830-013 2.6 -40 120 4.19 4.22 2.9 v bat rising v bat falling
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 38 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions general description the act5830's internal battery charger is an intelligent, stand-alone cc/cv (constant- current/constant-voltage), linear-mode single-cell charger for lithium-based cell-chemistries. this device incorporates current and voltage sense circuitry, an internal power mosfet, thermal- regulation circuitry, a complete state-machine to implement charge safety features, and circuitry that eliminates the reverse-blocking diode required by conventional charger designs. the act5830 battery charger operates independently of the regulators, and is automatically enabled whenever a valid input supply is available. the act5830's battery c harger features software- programmable fast-charge current, charge termination voltage, charge safety timeout period. the act5830's battery charger can accept input supplies in the 4.3v to 6v range, making it compatible with lower-voltage inputs such as 5-6v wall-cubes and usb ports. the battery charger, along with ldo1, ldo2, and ldo3, is enabled and initiates a charging cycle whenever an input supply is present. enabling/disabling the charger the act5830 is enabled when the voltage applied to chg_in is greater than the voltage at bat and is greater than 4.0v, and nenc hg is asserted low. the charger is disabled whenever nenchg is high, independent of the voltages at battery and chg_in. the charger may also be disabled via the i 2 c interface. for more information about enabling and disabling the charger, see the system startup & shutdown section. operation without a battery the act5830's charger is designed to operate with or without a battery connected. when a battery is connected, a normal charging cycle is performed as described below. if no battery is present, however, the charger will regulate the voltage at bat to the voltage programmed by chgr/vset[ _ ] to power the system. cc/cv regulation loop at the core of the act5830's battery charger is a cc/cv regulation loop, which regulates either current or voltage as necessary to ensure fast and safe charging of the battery. in a normal charge cycle, this loop regulates the current to the value set in the chgr/iset register. charging continues at this current until the battery cell voltage reaches the programmed termination voltage, as defined in the chgr/vset register. at this point the cv loop takes over, and charge current is allowed to decrease as necessary to maintain charging at the termination voltage. programming the char ge current (iset[ _ ]) in order to accommodate both usb and ac- powered inputs with a minimum of external components, the act5830 features a i 2 c- programmable fast-charge current that requires no external current-setting components. the chgr/iset register sets iset to any value greater than [0000] to program the maximum charge current to values in the 300ma to 1a via software. see for a detailed list of programmable charge currents. note that the actual charging current may be lower than the programmed fast-charge current, due to the act5830's thermal regulation loop. see the thermal regulation section for more information. measuring the charge current in order to ease monitoring of the charge current, the act5830 generates a voltage at vichg that is proportional to the charge current. the gain is typically 2.47mv/ma, and this voltage can be easily read by a system adc. vichg is high-impedance in shutdown. thermal regulation the act5830 features an internal thermal feedback loop that reduces the char ging current as necessary to ensure that the die temperature does not rise beyond the thermal regulation threshold of 115c. this feature protects the act5830 against accessing junction temperature, and allows the act5830 to be used in aggressive thermal designs without risk of damage. note that attention to good thermal design is still required to achieve the fastest possible charge time.
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 39 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? timoset [1:0 ] precondition timeout total charging timeout 0 0 1 hour 3 hours 0 1 1.43 hours 4.3 hours 1 0 2 hours 6 hours 1 1 infinite infinite functional descriptions cont?d charge safety timer while monitoring the charge cycle, the act5830 utilizes a charge safety timer to help identify damaged cells and to ensure that the cell is charged safely. three timeout options of 1 hour, 1.43 hours, and 2 hours are available, as programmed by the chgr/timoset register, and a timer-disable option is also available for systems that do not require the act5830 to control charge timeouts. the bit assignments for each timeout period are set as follows: table 12: timoset[ ] timeout period options chgr state-machine precondition state a new charging cycle begins with the precondition state. in this state, the cell is charged at a reduced current of 10% of iset, the programmed fast charge current. during a normal charge cycle, charging continues at this rate until v bat reaches the precondition threshold voltage of 2.9v (typ), at which po int the charging state machine jumps to its fast-charge state. if v bat does not reach the precondition threshold voltage before the precondition tim eout period expires, then a damaged cell is detected and the state machine jumps to the timeout-fault state. fast-charge state in fast-charge mode, the charger operates in constant-current (cc) mode and charges the cell at the current programmed by chgr/iset. during a normal charge cycle fast-charge continues until v bat reaches the termination voltage programmed by vset, at which point the state machine jumps to the topoff state. if vbat does not reach vset before the total time out period expires then the state-machine will jump to the ?sleep? state. top-off state in the top-off state, the cell is charged in constant-voltage (cv) mode. with the charge current limited by the internal chemistry of the cell, decreases as charging continues. during a normal charging cycle charging proceeds until the charge current decreases beyond the end-of-charge (eoc) threshold, defined as 10% of iset. when this happens, the state machine terminates the charge cycle and jumps to the sleep state. sleep state in sleep mode the act5830 presents a high- impedance to the battery, allowing the cell to ?relax? and minimizing battery leakage current. the act5830 continues to monitor the cell voltage, however, so that it can re-i nitiate charging cycles as necessary to ensure that the cell remains fully charged. under normal operation, the state machine initiates a new charging cycle by jumping to the fast-charge state when v bat drops below the charge termination threshold (programmed by vset) by more than the charge restart threshold of 200mv (typ). suspend state the act5830 features a user-selectable suspend- charge mode (suschg), which disables the charger but keeps other circuitry functional. charging continues in the suspend state until chgr/suspend is cleared, at which point the charge timer is reset and the state machine jumps to the precharge state. suspend charge by setting chgr/suschg = [1]. permit charging by cleari ng chgr/suschg to [0]. timeout-fault state in order to prevent continued operation with a damaged cell, there is no direct path to resume charging once a timeout fault occurs. in order to resume charging, the state machine must jump to the suspend state as a result of any of the following events: 1) microprocessor sets chgr/suschg to [1], 2) microprocessor pulls nenchg high, the input supply is removed or the input supply voltage drops below the uvlo threshold (4v), or the battery is removed. once any of these events occur, the state machine jumps to the suspend
single-cell li+ battery charger (chgr) act5830 rev 2, 20-jan-11 innovative power tm - 40 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? functional descriptions cont?d state and charging can resume as defined by figure 4. no bat state the act5830 charger has been designed so that it will provide system power wh en there is no battery present. if the battery is not present at any time while a valid input voltage (>4v) is applied to chg_in, the act5830 will enable the charger and regulate the output at the voltage programmed by chgr/vset[ ], simulating a battery-present condition. the output current of the charger in this state is default to 1000ma to ensure full operation of the phone. when operating in this state, the charge timers are disabled but the thermal regulation loop is active. it is important for the application designer to consider both the power available from the charger as well as the thermal design in order to ensure proper system operation in this state. the user c an prevent this operation by either: 1) pull nenchg high, or setting suschg = [1]. if the battery is reconnected while operating in the no bat state, the state machine resets the charge timers and jumps to the precondition state. reverse battery the act5830 includes internal circuitry that eliminates the need for series blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. when the input supply is removed, when vin goes below the act5830's under voltage-lockout (uvlo) voltage, or when vin drops below v bat , the act5830 automatically goes into suspend mode and reconfigures its power switch to minimize current drain from the battery. figure 4: charger state diagram precondition fast-charge top-off delay any state v chg_in < v bat or v chg_in < uvlo or chgr/suschg[ ] = [1] v bat > 2.9v v bat = vset[ ] v bat < vset[ ] ? 200mv i bat < iset[ ]/10 or t > timoset[ ] timeout-fault t > timoset[ ] and v bat < 2.9v sleep t > timoset[ ] t > 32ms battery present and v chg_in > v bat and v chg_in > uvlo and chgr/suschg[ ] = [0] ldo-mode suspend v b a t i d < 2 . 0 v v batid > 2.5v and v chg_in > uvlo and chgr/suschg[ ] = [0] any state i bat > iset[ ]/10 charge timers cleared charge timers not cleared or
package outline and dimensions act5830 rev 2, 20-jan-11 innovative power tm - 41 - www.active-semi.com copyright ? 2010 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of nxp. ? package outline tqfn55-40 package outline and dimensions symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.200 ref 0.008 ref b 0.150 0.250 0.006 0.010 d 4.900 5.100 0.193 0.201 e 4.900 5.100 0.193 0.201 d2 3.450 3.750 0.136 0.148 e2 3.450 3.750 0.136 0.148 e 0.400 bsc 0.016 bsc l 0.300 0.500 0.012 0.020 r 0.300 0.012 a1 a3 d2 e b l d d/2 e e/2 e2 a r active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com . ? is a registered trademark of active-semi.

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